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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. k 06/06/05 is61lv256 issi ? copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advise d to obtain the latest version of this device specification before relying on any published information and before placing orders for products. features ? high-speed access times: -- 8, 10, 12, 15 ns automatic power-down when chip is deselected cmos low power operation -- 345 mw (max.) operating -- 7 mw (max.) cmos standby ttl compatible interface levels single 3.3v power supply fully static operation: no clock or refresh required three-state outputs lead-free available description the issi is61lv256 is a very high-speed, low power, 32,768-word by 8-bit static ram. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. when ce is high (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 w (typical) with cmos input levels. easy memory expansion is provided by using an active low chip enable ( ce ). the active low write enable ( we ) controls both writing and reading of the memory. the is61lv256 is available in the jedec standard 28-pin, 300-mil soj and the 450-mil tsop (type i) packages. 32k x 8 low voltage cmos static ram june 2005 functional block diagram a0-a14 ce oe we 32k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7
is61lv256 issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 rev. k 06/06/05 pin configuration 28-pin soj 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 oe a11 a9 a8 a13 we vdd a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vdd we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 pin configuration 28-pin tsop (type i) pin descriptions a0-a14 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 input/output v dd power gnd ground truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc read h l l d out i cc write l l x d in i cc absolute maximum ratings (1) symbol parameter value unit v dd power supply voltage relative to gnd ?0.5 to +4.6 v v term terminal voltage with respect to gnd ?0.5 to +4.6 v t stg storage temperature ?65 to +150 c p d power dissipation 1 w i out dc output current 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
is61lv256 issi ? integrated silicon solution, inc. ? 1-800-379-4774 3 rev. k 06/06/05 dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?2.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 4.0 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?1 1 a ind. ?5 5 i lo output leakage gnd v out v dd , outputs disabled com. ?1 1 a ind. ?5 5 notes: 1. v il (min.) = ?0.3v (dc); v il (min.) = ?2.0v (pulse width 2.0 ns). v ih (max.) = v dd + 0.5v (dc); v ih (max.) = v dd + 2.0v (pulse width 2.0 ns). 2. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 5 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. operating range range ambient temperature speed (ns) v dd commercial 0c to +70c 8,10,12 3.3v, +10%, ?5% 15 3.3v 10% industrial ?40c to +85c 10,12 3.3v + 10%, ?5% power supply characteristics (1) (over operating range) -8 ns -10 ns -12 ns -15 ns sym. parameter test conditions min.max. min.max. min.max. min.max. unit i cc v dd dynamic operating v dd = max., ce = v il com. ? 120 ? 110 ? 100 ? 90 ma supply current i out = 0 ma, f = f max ind. ? ? ? 120 ? 110 ? 100 i sb 1 ttl standby current v dd = max., com. ? 15 ? 10 ? 10 ? 10 ma (ttl inputs) v in = v ih or v il ind. ? ? ? 20 ? 20 ? 20 ce v ih , f = 0 i sb 2 cmos standby v dd = max., com. ? 2 ? 2 ? 2 ? 2 ma current (cmos inputs) ce v dd ? 0.2v, ind. ? ? ? 5 ? 5 ? 5 v in v dd ? 0.2v, or v in 0.2v, f = 0 notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
is61lv256 issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 rev. k 06/06/05 ac test loads figure 1. figure 2. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 read cycle switching characteristics (1) (over operating range) -8 ns -10 ns -12 ns -15 ns symbol parameter min. max. min. max. min. max. min. max. unit t rc read cycle time 8 ? 10 ? 12 ? 15 ? ns t aa address access time ? 8 ? 10 ? 12 ? 15 ns t oha output hold time 2 ? 2 ? 2 ? 2 ? ns t ace ce access time ? 8 ? 10 ? 12 ? 15 ns t doe oe access time ? 4 ? 5 ? 6 ? 7 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? 0 ? ns t hzoe (2) oe to high-z output ? 4 ? 5 ? 5 ? 6 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? 3 ? ns t hzce (2) ce to high-z output ? 4 ? 5 ? 6 ? 7 ns t pu (3) ce to power-up 0 ? 0 ? 0 ? 0 ? ns t pd (3) ce to power-down ? 8 ? 10 ? 12 ? 15 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 200 mv from steady-state voltage. not 100% tested. 3. not 100% tested. 319 ? 30 pf including jig and scope 353 ? output 3.3v 319 ? 5 pf including jig and scope 353 ? output 3.3v
is61lv256 issi ? integrated silicon solution, inc. ? 1-800-379-4774 5 rev. k 06/06/05 data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2)
is61lv256 issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 rev. k 06/06/05 ac waveforms write cycle no. 1 ( ce controlled, oe is high or low) (1 ) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps write cycle switching characteristics (1,2) (over operating range) -8 ns -10 ns -12 ns -15 ns symbol parameter min. max. min. max. min. max. min. max. unit t wc write cycle time 8 ? 10 ? 12 ? 15 ? ns t sce ce to write end 6.5 ? 8 ? 8 ? 10 ? ns t aw address setup time 6.5 ? 8 ? 8 ? 10 ? ns to write end t ha address hold 0 ? 0 ? 0 ? 0 ? ns from write end t sa address setup time 0 ? 0 ? 0 ? 0 ? ns t pwe 1 we pulse width ( oe high) 6.5 ? 7 ? 8 ? 10 ? ns t pwe 2 we pulse width ( oe low) 8 ? 10 ? 12 ? 15 ? ns t sd data setup to write end 5 ? 5 ? 6 ? 7 ? ns t hd data hold from write end 0 ? 0 ? 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 3.5 ? 4 ? 6 ? 7 ns t lzwe (3) we high to low-z output 0 ? 0 ? 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
is61lv256 issi ? integrated silicon solution, inc. ? 1-800-379-4774 7 rev. k 06/06/05 data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps write cycle no. 2 ( we controlled, oe is high during write cycle) (1,2) write cycle no. 3 ( we controlled, oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v ih .
is61lv256 issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 rev. k 06/06/05 ordering information commercial range: 0c to +70c speed (ns) order part no. package 8 is61lv256-8t tsop - type i is61lv256-8j 300-mil plastic soj is61lv256-8jl 300-mil plastic soj, lead-free 10 IS61LV256-10T tsop - type i IS61LV256-10Tl tsop - type i, lead-free is61lv256-10j 300-mil plastic soj 12 is61lv256-12t tsop - type i is61lv256-12j 300-mil plastic soj is61lv256-12jl 300-mil plastic soj, lead free 15 is61lv256-15t tsop - type i is61lv256-15tl tsop - type i, lead free is61lv256-15j 300-mil plastic soj is61lv256-15jl 300-mil plastic soj, lead free ordering information industrial range: ?40c to +85c speed (ns) order part no. package 10 IS61LV256-10Ti tsop - type i is61lv256-10ji 300-mil plastic soj 12 is61lv256-12ti tsop - type i is61lv256-12tli tsop - type i, lead-free is61lv256-12ji 300-mil plastic soj is61lv256-12jli 300-mil plastic soj, lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 300-mil plastic soj package code: j notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches sym. min. typ. max. min. typ. max. n0. leads 24/26 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 17.02 17.27 0.670 0.680 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc seating plane 1 n e1 d e2 e b e a1 a b c a2
packaging information issi ? 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 millimeters inches sym. min. typ. max. min. typ. max. n0. leads 28 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 18.29 18.54 0.720 0.730 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc millimeters inches sym. min. typ. max. min. typ. max. n0. leads 32 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 20.83 21.08 0.820 0.830 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc 300-mil plastic soj package code: j
integrated silicon solution, inc. 1 issi packaging information d seating plane b e c 1 e a1 a s h l a n plastic tsop - 28-pins package code: t (type i) plastic tsop (ttype i) millimeters inches symbol min max min max ref. std. no. leads 28 a 1.00 1.20 0.037 0.047 a1 0.05 0.20 0.002 0.008 b 0.16 0.27 0.006 0.011 c 0.10 0.20 0.004 0.008 d 7.90 8.10 0.308 0.316 e 11.70 11.90 0.456 0.465 h 13.20 13.60 0.515 0.531 e 0.55 bsc 0.022 bsc l 0.30 0.70 0.011 0.027 a 0 5 0 5 notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. pk13197t28 rev. b 01/31/97

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